RTLScout Bench: how far can an LLM push hardware design?
Explore verified circuit designs, optimization progress and API costs in an interactive benchmark of LLM agents for RTL optimization.
How effectively can a language-model agent improve a digital circuit? RTLScout Bench lets you explore that question through measured hardware-design results.
Each model starts from a Verilog design and uses the RTLScout framework to propose and evaluate changes within a fixed step budget. A self-checking testbench and synthesis flow evaluate the candidates. The dashboard compares the best verified results, progress during optimization and API spending.
The main objective is the area-delay product: circuit area multiplied by critical-path delay. Lower values indicate better throughput per unit of silicon for the benchmark's fixed cycle counts. Interactive charts show individual runs alongside aggregate results, making variability and the trade-off between optimization quality and cost visible.
The research behind RTLScout
The RTLScout paper, by Felix Arnold, Ryan Amaudruz, Dimitrios Tsaras, Renzo Andri and Lukas Cavigelli, combines agent-driven code optimization with logic synthesis and arithmetic architecture selection. Its Spire hardware-description language allows optimization choices to be expressed locally in the source.
Visit the benchmark dashboard, explore the RTLScout code, or inspect the benchmark repository.