Beyond Equivalence: Task-Level Verification Unlocks Architectural Optimizations by LLM Agents
Abstract
Automated RTL optimization is conventionally verified by logical equivalence. The optimized design must reproduce the reference's cycle-by-cycle I/O behavior, which fixes the schedule and the memory access pattern. We relax the verification contract to the ask level, where the only requirement is correctness of the output data for given input data, leaving the cycle schedule, memory access order, and internal architecture free. On six benchmarks ranging from matrix multiplication to a RISC-V ALU, an LLM optimization agent improves the baseline RTL design under both formulations. We compare the achieved cost using cycle-aware metrics: area-runtime product and its energy-weighted extension, where energy is the measured circuit energy for a given workload. Equivalence-constrained optimization reduces cost by up to 57%, while task-level freedom reaches up to 82%. The measured workload energy decreases by up to 31% under equivalence and up to 90% with task-level freedom. A further analysis on the matrix-multiplication benchmark weights the cost by data-movement count and shows that an exponent on the movement term acts as a dial over the accelerator design space, steering the optimal architecture from a single multiplier through operand-reuse tiles to a fully buffered parallel array.
