Practically Tackling Memory Bottlenecks of Graph-Processing Workloads

Abstract summary

Graph workloads often have irregular memory references that gain little from traversing the conventional cache hierarchy. This work predicts access regularity using instruction-level stride information. Regular requests follow the usual path, while irregular requests use a small cache beside the first-level data cache and bypass lower cache levels. The design aims to reduce latency and cache contention without changing application code or preprocessing graph inputs.

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@misc{practicallytacklingmemorybottlenecksofgraphprocessingworkloads,
  title = {Practically Tackling Memory Bottlenecks of Graph-Processing Workloads},
  author = {Alexandre Valentin Jamet and Georgios Vavouliotis and Daniel A. Jiménez and Lluc Alvarez and Marc Casas},
  year = {2024},
  note = {IPDPS},
  url = {https://doi.org/10.1109/ipdps57955.2024.00096}
}

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