Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources

Abstract

Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs).

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@misc{victimadrasticallyincreasingaddresstranslationreachbyleveragingunderutilizedcacheresources,
  title = {Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources},
  author = {Konstantinos Kanellopoulos and Hong Chul Nam and Nisa Bostanci and Rahul Bera and Mohammad Sadrosadati and Rakesh Kumar and Davide Basilio Bartolini and Onur Mutlu},
  year = {2023},
  note = {MICRO},
  url = {https://doi.org/10.1145/3613424.3614276}
}

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